]> git.baikalelectronics.ru Git - kernel.git/commit
drm/i915/dp: cache common rates with sink rates
authorJani Nikula <jani.nikula@intel.com>
Thu, 6 Apr 2017 13:44:10 +0000 (16:44 +0300)
committerJani Nikula <jani.nikula@intel.com>
Tue, 11 Apr 2017 13:54:30 +0000 (16:54 +0300)
commit47726271d97bb8263e433ae9503682aeadd7e86e
tree1d00e633400cf231212fbc08918b93f1523ac634
parent54faa5989d9c820d8f33cc95fb4cbb1690b0ff13
drm/i915/dp: cache common rates with sink rates

Now that source rates are static and sink rates are updated whenever
DPCD is updated, we can do and cache the intersection of them whenever
sink rates are updated. This reduces code complexity, as we don't have
to keep calling the functions to intersect. We also get rid of several
common rates arrays on stack.

Limiting the common rates by a max link rate can be done by picking the
first N elements of the cached common rates.

v2: get rid of the local common_rates variable (Manasi)
v3: don't clobber cached eDP rates on short pulse (Ville)

Cc: Manasi Navare <manasi.d.navare@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/e3b287e8cb6559b1f8fd4e80b78a8d22f1802eb7.1491485983.git.jani.nikula@intel.com
drivers/gpu/drm/i915/intel_dp.c
drivers/gpu/drm/i915/intel_drv.h