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(parent: 9687afc) | patch
drm/msm/a6xx: Send the right perf index value to GMU
authorSharat Masetty <smasetty@codeaurora.org>
Thu, 27 Sep 2018 16:46:22 +0000 (22:16 +0530)
committerRob Clark <robdclark@gmail.com>
Thu, 4 Oct 2018 00:24:54 +0000 (20:24 -0400)
commit408c0862734e62beb4938137bd513b43c3baefd4
tree0f9aa5738480512e3593cfd321869bf70e8bc133tree | snapshot
parent9687afc16305b0cbb552067966e6fb34252427f7commit | diff
drm/msm/a6xx: Send the right perf index value to GMU

The index of the perf table was being set in the wrong bit position
in the register. With this fix, the GPU clock can be seen running at
desired frequency.

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
drivers/gpu/drm/msm/adreno/a6xx_gmu.c diff | blob | history
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