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(parent: 4333c72) | patch
drm/i915/ringbuffer: exclude last 2 cachelines on 845g on all callpaths
authorMika Kuoppala <mika.kuoppala@linux.intel.com>
Mon, 29 Oct 2012 14:59:26 +0000 (16:59 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Sun, 11 Nov 2012 22:51:09 +0000 (23:51 +0100)
commit3e94e342ea12b573848c6000a7323acf521043e1
treedc514c52a0091c6212afd2a9d188e45f706c733ctree | snapshot
parent4333c72b3fde2f922f6518244cdaad8a976a0f8fcommit | diff
drm/i915/ringbuffer: exclude last 2 cachelines on 845g on all callpaths

Make intel_render_ring_init_dri and intel_init_ring_buffer symmetrical
with regards of workaround introduced by:

commit f13c47d701bfeaa264a2111de35333b180c511b1
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Mon Apr 9 13:59:46 2012 +0100

    drm/i915/ringbuffer: Exclude last 2 cachlines of ring on 845g

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_ringbuffer.c diff | blob | history
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