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Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"
authorMika Kuoppala <mika.kuoppala@linux.intel.com>
Wed, 6 May 2020 14:47:31 +0000 (17:47 +0300)
committerChris Wilson <chris@chris-wilson.co.uk>
Thu, 7 May 2020 06:44:40 +0000 (07:44 +0100)
commit35fac06051c41200486fe5bbe5da585add3dd6f0
tree8c26324826f1e9eecb0f3cd6218e444a2f02da4etree | snapshot
parent65f42bf8997b800b5562b3d53b9b8b147766aa3bcommit | diff
Revert "drm/i915/tgl: Include ro parts of l3 to invalidate"

This reverts commit 9eee72094f8ac00235a7fdb6fa11fb9c966d8624.

L3 ro cache invalidation is part of the dword0 of pipe
control. Also it is not relevant to this gen.

Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200506144734.29297-1-mika.kuoppala@linux.intel.com
drivers/gpu/drm/i915/gt/intel_gpu_commands.h diff | blob | history
drivers/gpu/drm/i915/gt/intel_lrc.c diff | blob | history
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