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(parent: 4758043) | patch
drm/i915: Add CxSR support on Pineview DDR3
authorLi Peng <peng.li@linux.intel.com>
Tue, 18 May 2010 10:58:44 +0000 (18:58 +0800)
committerEric Anholt <eric@anholt.net>
Wed, 26 May 2010 21:22:51 +0000 (14:22 -0700)
commit34f8f3ecc922633217137ba99c66a6e3663b7666
tree8df1e5e08fd759c2c7279c232ef7e6732a3e65dbtree | snapshot
parent47580432656c178eab311b7f0fe1fe7601c8fe7acommit | diff
drm/i915: Add CxSR support on Pineview DDR3

Pineview with DDR3 memory has different latencies to enable CxSR.
This patch updates CxSR latency table to add Pineview DDR3 latency
configuration. It also adds one flag "is_ddr3" for checking DDR3
setting in MCHBAR.

Cc: Shaohua Li <shaohua.li@intel.com>
Cc: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Li Peng <peng.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
drivers/gpu/drm/i915/i915_dma.c diff | blob | history
drivers/gpu/drm/i915/i915_drv.h diff | blob | history
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
drivers/gpu/drm/i915/intel_display.c diff | blob | history
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