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(parent: 2a0dca7) | patch
RISC-V: Comment on why {,cmp}xchg is ordered how it is
authorPalmer Dabbelt <palmer@sifive.com>
Tue, 28 Nov 2017 22:02:50 +0000 (14:02 -0800)
committerPalmer Dabbelt <palmer@sifive.com>
Tue, 28 Nov 2017 22:03:29 +0000 (14:03 -0800)
commit330c590c2024c32af9b827f9cad9d6069c2e0172
tree6c54619aa865b731d9682c39cc27e40d65090fd0tree | snapshot
parent2a0dca762f964546334e27e4a5323df9a45f50e3commit | diff
RISC-V: Comment on why {,cmp}xchg is ordered how it is

This is another memory model FIXME.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
arch/riscv/include/asm/atomic.h diff | blob | history
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