]> git.baikalelectronics.ru Git - kernel.git/commit
platform/x86: intel_pmc_ipc: read s0ix residency API
authorShanth Murthy <shanth.murthy@intel.com>
Mon, 13 Feb 2017 12:02:52 +0000 (04:02 -0800)
committerDarren Hart <dvhart@linux.intel.com>
Sat, 25 Feb 2017 07:48:46 +0000 (23:48 -0800)
commit3084078e029324c102d7b658214d54e5dee698ef
treea31fec0f30185a87d7a26bb370c1bd8d5c842e3e
parentc2b7a53e3b144b4e9a559a48cfa9161429560d77
platform/x86: intel_pmc_ipc: read s0ix residency API

This patch adds a new API to indicate S0ix residency in usec. It utilizes
the PMC Global Control Registers (GCR) to read deep and shallow
S0ix residency.

PMC MMIO resources:
        o Lower 4kB: IPC1 (PMC inter-processor communication) interface
        o Upper 4kB: GCR (Global Control Registers)

This enables the power management framework to take corrective actions when
the platform fails to enter S0ix after kernel freeze as part of the suspend
to idle flow. (echo freeze > /sys/power/state).

This is expected to be used with a S0ix failsafe framework such as:
<https://lwn.net/Articles/689505/>

[rajneesh: folded in "fix division in 32-bit case" from Andy Shevchenko]
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Signed-off-by: Shanth Murthy <shanth.murthy@intel.com>
[andy: fixed kbuild error, removed "total" from variables, fixed macro]
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
arch/x86/include/asm/intel_pmc_ipc.h
drivers/platform/x86/intel_pmc_ipc.c