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(parent: e1a4b67) | patch
drm/amdgpu/gfx10: update CGTS_TCC_DISABLE and CGTS_USER_TCC_DISABLE register offsets...
authorchen gong <curry.gong@amd.com>
Fri, 29 Jan 2021 07:37:45 +0000 (15:37 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 2 Feb 2021 17:06:29 +0000 (12:06 -0500)
commit2cb96b238701aae8d86bb63ba19eaeb34f5bfa26
tree94cf79499904c6b71628c3e12b283b15b74deacbtree | snapshot
parente1a4b67aac9ee870b4d95a008d47910c47db3092commit | diff
drm/amdgpu/gfx10: update CGTS_TCC_DISABLE and CGTS_USER_TCC_DISABLE register offsets for VGH

For Vangogh:
The offset of the CGTS_TCC_DISABLE is 0x5006 by calculation.
The offset of the CGTS_USER_TCC_DISABLE is 0x5007 by calculation.

Signed-off-by: chen gong <curry.gong@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c diff | blob | history
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