drm/amd/display: dc/dce: add initial DCE6 support (v10)

drm/amd/display: dc/dce: add initial DCE6 support (v10)

[Why]
DCE6 chipsets have a lot in common with DCE8, let's start from this

[How]
DCE6 targets are added replicating existing DCE8 implementation.

NOTE: dce_8_0_{d,sh_mask}.h headers used instead of dce_6_0_{d,sh_mask}.h
initial build prototype due to missing DCE6 macros/registers/masks
DCE6 specific macros/registers/masks will be added with later commits

(v2b) removed dce_version cases in dc/dce/dce_clock_source.c and
     updated dce60 due to following kernel 5.0 commits:
     c534519 ("drm/amd/display: move pplib/smu notification to dccg block")
     99902cd ("drm/amd/display: remove safe_to_lower flag from dc, use 2 functions instead")
     a647f94 ("drm/amd/display: clean up base dccg struct")
     de6a494 ("drm/amd/display: split dccg clock manager into asic folders")
     d59b6ef ("drm/amd/display: rename dccg to clk_mgr")
     50c67a4 ("drm/amd/display: Remove duplicate header")
     ef15648 ("drm/amd/display: fix optimize_bandwidth func pointer for dce80")
     f4112dd ("drm/amd/display: set clocks to 0 on suspend on dce80")

(v3b) updated dce60 due to following kernel 5.1 commits:
     a06087b ("drm/amd/display: Use 100 Hz precision for pipe pixel clocks")
     b9a7ed7 ("drm/amd/display: Fix 64-bit division for 32-bit builds")
     b5dd424 ("drm/amd/display: Change from aux_engine to dce_aux")
     5712591 ("drm/amd/display: fix eDP fast bootup for pre-raven asic")

(v4b) updated dce60 due to following kernel 5.2 commits:
     0961032 ("drm/amd/display: Add plane capabilities to dc_caps")
     9f76b8f ("drm/amd/display: Fix multi-thread writing to 1 state")
     696f19a ("drm/amd/display: expand plane caps to include fp16 and scaling capability")
     57edecf ("drm/amd/display: Add fast_validate parameter")

(v5b) updated dce60 due to following kernel 5.3 commits:
     a050c0f ("drm/amd/display: stop external access to internal optc sync params")
     a919bad ("drm/amd/display: Engine-specific encoder allocation")
     70531f9 ("drm/amd/display: make clk mgr soc specific")
     3016edd ("drm/amd: drop use of drmp.h in os_types.h")

(v6b) updated dce60 due to following kernel 5.4 commits:
     d8333f6 ("drm/amd/display: Fix a typo - dce_aduio_mask --> dce_audio_mask")
     82d0f62 ("drm/amd/display: make firmware info only load once during dc_bios create")

(v7b) updated dce60 due to following kernel 5.5 commits:
     3bbb9d1 ("drm/amd/display: memory leak")
     e62b58c ("drm/amd/display: update register field access mechanism")
     c64e6da ("drm/amd/display: configurable aux timeout support")
     437e79a ("drm/amd/display: map TRANSMITTER_UNIPHY_x to LINK_REGS_x")

(v8b) updated dce60 due to following kernel 5.6 commits:
     70cdea6 ("drm/amd/display: cleanup of construct and destruct funcs")
     1db1b05 ("drm/amd/display: add separate of private hwss functions")

(v9b) updated dce60 due to following kernel 5.8 commits:
     af44b1e ("drm/amd/display: code clean up in dce80_hw_sequencer.c")
     ae5c1ca ("drm/amd/display: move panel power seq to new panel struct")
     9cbfdde ("drm/amd/display: change from panel to panel cntl")

(v10) Fix up PLL handling for DCE6:
     DCE6.0 supports 2 PLLs.  DCE6.1 supports 3 PLLs. (Alex)

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>