]> git.baikalelectronics.ru Git - arm-tf.git/commit
Workaround for Cortex N1 erratum 1946160
authorjohpow01 <john.powell@arm.com>
Wed, 7 Oct 2020 19:33:15 +0000 (14:33 -0500)
committerJohn <john.powell@arm.com>
Wed, 13 Jan 2021 19:56:07 +0000 (19:56 +0000)
commit263ee781c6805172386686b65d012d188a842f05
tree291c5201b55c5bfe71308a6201c624f612650b00
parent3a2710dcab0dc6dc625f0a4956a44bace1788618
Workaround for Cortex N1 erratum 1946160

Cortex N1 erratum 1946160 is a Cat B erratum present in r0p0, r1p0,
r2p0, r3p0, r3p1, r4p0, and r4p1.  The workaround is to insert a DMB ST
before acquire atomic instructions without release semantics.  This
issue is present starting from r0p0 but this workaround applies to
revisions r3p0, r3p1, r4p0, and r4p1, for previous revisions there is no
workaround.

SDEN can be found here:
https://documentation-service.arm.com/static/5fa9304cd8dacc30eded464f

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I36e4d6728c275f1c2477dcee9b351077cf7c53e4
docs/design/cpu-specific-build-macros.rst
lib/cpus/aarch64/neoverse_n1.S
lib/cpus/cpu-ops.mk