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(parent: 289710a) | patch
clk: socfpga: Support multiple parents for the pll clocks
authorDinh Nguyen <dinguyen@altera.com>
Wed, 19 Feb 2014 21:11:11 +0000 (15:11 -0600)
committerMike Turquette <mturquette@linaro.org>
Wed, 26 Feb 2014 20:23:40 +0000 (12:23 -0800)
commit24d9686224b895e1a9cf4a78700d82a1d5973ca3
tree711a1ada6d863af2fe3f8022d27820c7bd479a0etree | snapshot
parent289710a6cbf8b8493a302e855480b4b67a464efbcommit | diff
clk: socfpga: Support multiple parents for the pll clocks

The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk.
Update the clock driver to be able to get the correct parent.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
drivers/clk/socfpga/clk-pll.c diff | blob | history
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