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(parent: b9a23e7) | patch
drm/nouveau/disp/sor/gf119: both links use the same training register
authorBen Skeggs <bskeggs@redhat.com>
Fri, 3 Jun 2016 04:37:40 +0000 (14:37 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Mon, 6 Jun 2016 22:11:14 +0000 (08:11 +1000)
commit2188911ece49216a3c2436018104d2c2395cdba0
tree210fe44ee38c2cfcd0741f444e94288dffdb6709tree | snapshot
parentb9a23e766516b480e2df653e073b175cb60f45a6commit | diff
drm/nouveau/disp/sor/gf119: both links use the same training register

It appears that, for whatever reason, both link A and B use the same
register to control the training pattern.  It's a little odd, as the
GPUs before this (Tesla/Fermi1) have per-link registers, as do newer
GPUs (Maxwell).

Fixes the third DP output on NVS 510 (GK107).

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
drivers/gpu/drm/nouveau/nvkm/engine/disp/sorgf119.c diff | blob | history
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