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(parent: b1803e2) | patch
CLK: HSDK: CGU: support PLL bypassing
authorEugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Wed, 11 Mar 2020 13:41:14 +0000 (16:41 +0300)
committerStephen Boyd <sboyd@kernel.org>
Fri, 29 May 2020 04:06:39 +0000 (21:06 -0700)
commit201b2c35968e5a6a35247c476c81729f6d1c213c
tree95d885366b94eed939670a5e2fa0599fe9ab8232tree | snapshot
parentb1803e23f7aa1fcd04d379e43b7b97c9ba4404fdcommit | diff
CLK: HSDK: CGU: support PLL bypassing

Support setting PLL to bypass mode to support output frequency
equal to input one.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Link: https://lkml.kernel.org/r/20200311134115.13257-3-Eugeniy.Paltsev@synopsys.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/clk-hsdk-pll.c diff | blob | history
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