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(parent: ca75d24) | patch
ARM: pxa168: correct nand pmu setting
authorLei Wen <leiwen@marvell.com>
Tue, 21 Jun 2011 12:37:47 +0000 (05:37 -0700)
committerEric Miao <eric.y.miao@gmail.com>
Wed, 6 Jul 2011 15:51:36 +0000 (23:51 +0800)
commit1e934d0a7ff6b418e30a181808d5aab0770d3f73
tree7f534aced1211babfa537d5b1c2e5ebbc7e4566btree | snapshot
parentca75d24c3eb86211cb7f19a53df042b9ad323e9fcommit | diff
ARM: pxa168: correct nand pmu setting

The original pair of <0x01db, 208000000> is invalid. Correct it to
the valid value.

The 6th bit of the NFC APMU register indicates NFC works whether
at 156Mhz or 78Mhz. So 0x19b indicates NFC works at 156Mhz, and
0x1db indicates it works at 78Mhz.

Signed-off-by: Lei Wen <leiwen@marvell.com>
Cc: stable@kernel.org
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
arch/arm/mach-mmp/pxa168.c diff | blob | history
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