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(parent: db7cfd8) | patch
i915: Map status page cached for chips with GTT-based HWS location.
authorKeith Packard <keithp@keithp.com>
Wed, 15 Oct 2008 02:55:10 +0000 (19:55 -0700)
committerDave Airlie <airlied@linux.ie>
Fri, 17 Oct 2008 21:10:53 +0000 (07:10 +1000)
commit1d056508d485934140642d9daf68f2ccc410e834
tree73b45769022788532ee169c270e2792a229b1a40tree | snapshot
parentdb7cfd83bdf0efcb692dbe8b5a06e50386652f90commit | diff
i915: Map status page cached for chips with GTT-based HWS location.

This should improve performance by avoiding uncached reads by the CPU (the
point of having a status page), and may improve stability.  This patch only
affects G33, GM45 and G45 chips as those are the only ones using GTT-based
HWS mappings.

Signed-off-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/drm_agpsupport.c diff | blob | history
drivers/gpu/drm/i915/i915_drv.h diff | blob | history
drivers/gpu/drm/i915/i915_gem.c diff | blob | history
include/drm/drmP.h diff | blob | history
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