]> git.baikalelectronics.ru Git - kernel.git/commit
MIPS: smp-cps: Skip core setup if coherent
authorPaul Burton <paul.burton@imgtec.com>
Wed, 3 Feb 2016 03:15:32 +0000 (03:15 +0000)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 13 May 2016 12:01:50 +0000 (14:01 +0200)
commit1c77df09da2801b4ad3a8e03590a0b1055aa9859
treeaf92be6eadac4c5363881d68ee36954ded88b2ad
parent12e8e52cd60acf6349cb6c15e18b877b711eaca0
MIPS: smp-cps: Skip core setup if coherent

In preparation for supporting MIPSr6 multithreading (ie. VPs) which will
begin execution from the core reset vector, skip core level setup if the
core is already coherent. This is never the case when a core is first
started, since boot_core explicitly clears the cores GCR_Cx_COH_EN
register, and always the case when secondary VPs start since the first
VP to start will have enabled coherence after initialising the core &
its caches.

One notable side effect of this patch is that eva_init gets called
slightly earlier, prior to mips_cps_core_init rather than after it.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12338/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/kernel/cps-vec.S