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(parent: 8d1197f) | patch
drm/nouveau/falcon: fix base address of FBIF registers
authorAlexandre Courbot <acourbot@nvidia.com>
Thu, 26 Jan 2017 07:49:43 +0000 (16:49 +0900)
committerBen Skeggs <bskeggs@redhat.com>
Tue, 7 Mar 2017 07:05:13 +0000 (17:05 +1000)
commit1c4ba8e2575b8b7bca75f238810ef6c586f8e58f
treeb32d65654f367799b149ad755e954fe259465aa4tree | snapshot
parent8d1197fb3e4f5e19ca1316cc4d88e82ebdfb0252commit | diff
drm/nouveau/falcon: fix base address of FBIF registers

All falcons have their FBIF registers starting at offset 0x600, with the
exception of the PMU and NVENC engines.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nvkm/falcon/v1.c diff | blob | history
Linux Kernel Source Tree.