]> git.baikalelectronics.ru Git - kernel.git/commit
dt-bindings: msm/dsi: Add 10nm dsi phy tuning properties
authorRajeev Nandan <quic_rajeevny@quicinc.com>
Sun, 30 Jan 2022 20:15:17 +0000 (01:45 +0530)
committerDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fri, 18 Feb 2022 15:32:59 +0000 (18:32 +0300)
commit1301131b629596b89e9eace2517dab9ec6da2b9c
tree6bfe5e1b3c009e3414c6d296cd4d06c3ed47acb8
parentc59443c43b00986ad05d61fd0309b1b0a13a2909
dt-bindings: msm/dsi: Add 10nm dsi phy tuning properties

In most cases, the default values of DSI PHY tuning registers should be
sufficient as they are fully optimized. However, in some cases where
extreme board parasitics cause the eye shape to degrade, the override
bits can be used to improve the signal quality.

The general guidelines for DSI PHY tuning include:
- High and moderate data rates may benefit from the drive strength and
  drive level tuning.
- Drive strength tuning will affect the output impedance and may be used
  for matching optimization.
- Drive level tuning will affect the output levels without affecting the
  impedance.

The clock and data lanes have a calibration circuitry feature. The drive
strength tuning can be done by adjusting rescode offset for hstop/hsbot,
and the drive level tuning can be done by adjusting the LDO output level
for the HSTX drive.

Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1643573719-32095-2-git-send-email-quic_rajeevny@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml