]> git.baikalelectronics.ru Git - kernel.git/commit
Revert "riscv: mm: notify remote harts about mmu cache updates"
authorSergey Matyukevich <sergey.matyukevich@syntacore.com>
Sun, 26 Feb 2023 15:01:36 +0000 (18:01 +0300)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 22 Mar 2023 12:34:00 +0000 (13:34 +0100)
commit0f12d840ae656693fc1e1516f1ce1577075251ff
treea77153e89cf85ac23dc2811428d29eb6ab7fadf1
parentd856598c8d5ac1dbc48b2fae335edac5836bf0fe
Revert "riscv: mm: notify remote harts about mmu cache updates"

commit 1fb567bb185923bbcd33373cc699809e8369841d upstream.

This reverts the remaining bits of commit 88329b081509 ("riscv: mm:
notify remote harts harts about mmu cache updates").

According to bug reports, suggested approach to fix stale TLB entries
is not sufficient. It needs to be replaced by a more robust solution.

Fixes: 88329b081509 ("riscv: mm: notify remote harts about mmu cache updates")
Reported-by: Zong Li <zong.li@sifive.com>
Reported-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Cc: stable@vger.kernel.org
Reviewed-by: Guo Ren <guoren@kernel.org>
Link: https://lore.kernel.org/r/20230226150137.1919750-2-geomatsi@gmail.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/riscv/include/asm/mmu.h
arch/riscv/include/asm/tlbflush.h
arch/riscv/mm/context.c
arch/riscv/mm/tlbflush.c