]> git.baikalelectronics.ru Git - kernel.git/commit
drm/amd/display: limit display clock to 100MHz to avoid FIFO error
authorYu-ting Shen <Yu-ting.Shen@amd.com>
Fri, 7 Feb 2020 07:19:31 +0000 (15:19 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 25 Feb 2020 16:10:08 +0000 (11:10 -0500)
commit0d2766b767bb357aba2093c60b03e0a6869fc263
treefde65b894009996b7a244bd03c449e43967b0b8b
parentc20ee005de863ba038ea8b9d3ee94159f53df2e3
drm/amd/display: limit display clock to 100MHz to avoid FIFO error

[Why]
when changing display clock, SMU need to use power up DFS and use
DENTIST to ramp DFS DID to switch target frequency before switching back
to bypass.

[How]
fixed the minimum display clock to 100MHz, it's W/A the same with PCO.

Signed-off-by: Yu-ting Shen <Yu-ting.Shen@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c