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ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)
authorVineet Gupta <vgupta@synopsys.com>
Fri, 3 Apr 2015 09:37:07 +0000 (12:37 +0300)
committerVineet Gupta <vgupta@synopsys.com>
Thu, 25 Jun 2015 00:30:19 +0000 (06:00 +0530)
commit070b9cc20106293823ab8c0e1bce90e94cf3c098
treeb4cb8211acf56f2f8acc7ef1429cee4e667f2834tree | snapshot
parent2b898004daf2fbc8e68e81a996d0b79db3cf856acommit | diff
ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)

L2 cache on ARCHS processors is called SLC (System Level Cache)
For working DMA (in absence of hardware assisted IO Coherency) we need
to manage SLC explicitly when buffers transition between cpu and
controllers.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
arch/arc/include/asm/cache.h diff | blob | history
arch/arc/mm/cache.c diff | blob | history
arch/arc/mm/dma.c diff | blob | history
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