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clk: at91: sama7g5: fix parents of PDMCs' GCLK
authorCodrin Ciubotariu <codrin.ciubotariu@microchip.com>
Fri, 4 Mar 2022 18:26:16 +0000 (20:26 +0200)
committerNicolas Ferre <nicolas.ferre@microchip.com>
Tue, 8 Mar 2022 14:35:35 +0000 (15:35 +0100)
commit0644df43bc2675062b41693bd15f855e931688a6
tree69000ad631b27030be93d0e1eaccfa733f6d6a81tree | snapshot
parent78f4e6ef1637c27384434f068add05f19d2bc120commit | diff
clk: at91: sama7g5: fix parents of PDMCs' GCLK

Audio PLL can be used as parent by the GCLKs of PDMCs.

Fixes: 2860a5859839 ("clk: at91: sama7g5: add clock support for sama7g5")
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220304182616.1920392-1-codrin.ciubotariu@microchip.com
drivers/clk/at91/sama7g5.c diff | blob | history
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