]> git.baikalelectronics.ru Git - kernel.git/commit
MIPS: Lantiq: Fix ASC0/ASC1 clocks
authorMartin Schiller <ms@dev.tdt.de>
Tue, 30 May 2017 04:34:34 +0000 (06:34 +0200)
committerJames Hogan <jhogan@kernel.org>
Tue, 7 Nov 2017 22:40:15 +0000 (22:40 +0000)
commit0563b0baf1e7347d059b7db0f96c6088051972fc
tree3d5a8b5133e05c3e8e0bbc69ef485c9ae9fdd1bb
parent3f6afada98add71971b6e830af15c589358166b5
MIPS: Lantiq: Fix ASC0/ASC1 clocks

ASC1 is available on every Lantiq SoC (also AmazonSE) and should be
enabled like the other generic xway clocks instead of ASC0, which is
only available for AR9 and Danube.

Signed-off-by: Martin Schiller <ms@dev.tdt.de>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: John Crispin <john@phrozen.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Felix Fietkau <nbd@nbd.name>
Cc: Martin Schiller <ms@dev.tdt.de>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/16145/
[jhogan@kernel.org: Drop braces]
Signed-off-by: James Hogan <jhogan@kernel.org>
arch/mips/lantiq/xway/sysctrl.c