]> git.baikalelectronics.ru Git - kernel.git/commit
drm/amd/display: Correct DML calculation to follow HW SPEC
authorPaul Hsieh <Paul.Hsieh@amd.com>
Wed, 22 Mar 2023 09:46:31 +0000 (17:46 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 24 May 2023 16:32:36 +0000 (17:32 +0100)
commit03e295ade7e34ff628c2433cd711da7b501103a3
tree63ae63580489d3d1e5096e954b921ede5285f154
parent71f6fe4e991d5b26a7bf9c61234b95564a04ee43
drm/amd/display: Correct DML calculation to follow HW SPEC

[ Upstream commit 385c3e4c29e1d4ce8f68687a8c84621e4c0e0416 ]

[Why]
In 2560x1600@240p eDP panel, driver use lowest voltage level
to play 1080p video cause underflow. According to HW SPEC,
the senario should use high voltage level.

[How]
ChromaPre value is zero when bandwidth validation.
Correct ChromaPre calculation.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Paul Hsieh <Paul.Hsieh@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c