]> git.baikalelectronics.ru Git - kernel.git/commit
drm: Add support for the LogiCVC display controller
authorPaul Kocialkowski <paul.kocialkowski@bootlin.com>
Fri, 20 May 2022 14:15:55 +0000 (16:15 +0200)
committerPaul Kocialkowski <paul.kocialkowski@bootlin.com>
Thu, 9 Jun 2022 14:49:56 +0000 (16:49 +0200)
commit03b72aa1419afac258ab53702e31c9bc377f4752
treefd6f9768de34219c02f0186f5c188d663fc19bb6
parent291a8658324c159bc90f27050a02719594d4adc7
drm: Add support for the LogiCVC display controller

Introduces a driver for the LogiCVC display controller, a programmable
logic controller optimized for use in Xilinx Zynq-7000 SoCs and other
Xilinx FPGAs. The controller is mostly configured at logic synthesis
time so only a subset of configuration is left for the driver to
handle.

The following features are implemented and tested:
- LVDS 4-bit interface;
- RGB565 pixel formats;
- Multiple layers and hardware composition;
- Layer-wide alpha mode;

The following features are implemented but untested:
- Other RGB pixel formats;
- Layer framebuffer configuration for version 4;
- Lowest-layer used as background color;
- Per-pixel alpha mode.

The following features are not implemented:
- YUV pixel formats;
- DVI, LVDS 3-bit, ITU656 and camera link interfaces;
- External parallel input for layer;
- Color-keying;
- LUT-based alpha modes.

Additional implementation-specific notes:
- Panels are only enabled after the first page flip to avoid flashing a
  white screen.
- Depth used in context of the LogiCVC driver only counts color components
  to match the definition of the synthesis parameters.

Support is implemented for both version 3 and 4 of the controller.

With version 3, framebuffers are stored in a dedicated contiguous
memory area, with a base address hardcoded for each layer. This requires
using a dedicated CMA pool registered at the base address and tweaking a
few offset-related registers to try to use any buffer allocated from
the pool. This is done on a best-effort basis to have the hardware cope
with the DRM framebuffer allocation model and there is no guarantee
that each buffer allocated by GEM CMA can be used for any layer.
In particular, buffers allocated below the base address for a layer are
guaranteed not to be configurable for that layer. See the implementation of
logicvc_layer_buffer_find_setup for specifics.

Version 4 allows configuring each buffer address directly, which
guarantees that any buffer can be configured.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Maxime Ripard <mripard@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20220520141555.1429041-2-paul.kocialkowski@bootlin.com
18 files changed:
MAINTAINERS
drivers/gpu/drm/Kconfig
drivers/gpu/drm/Makefile
drivers/gpu/drm/logicvc/Kconfig [new file with mode: 0644]
drivers/gpu/drm/logicvc/Makefile [new file with mode: 0644]
drivers/gpu/drm/logicvc/logicvc_crtc.c [new file with mode: 0644]
drivers/gpu/drm/logicvc/logicvc_crtc.h [new file with mode: 0644]
drivers/gpu/drm/logicvc/logicvc_drm.c [new file with mode: 0644]
drivers/gpu/drm/logicvc/logicvc_drm.h [new file with mode: 0644]
drivers/gpu/drm/logicvc/logicvc_interface.c [new file with mode: 0644]
drivers/gpu/drm/logicvc/logicvc_interface.h [new file with mode: 0644]
drivers/gpu/drm/logicvc/logicvc_layer.c [new file with mode: 0644]
drivers/gpu/drm/logicvc/logicvc_layer.h [new file with mode: 0644]
drivers/gpu/drm/logicvc/logicvc_mode.c [new file with mode: 0644]
drivers/gpu/drm/logicvc/logicvc_mode.h [new file with mode: 0644]
drivers/gpu/drm/logicvc/logicvc_of.c [new file with mode: 0644]
drivers/gpu/drm/logicvc/logicvc_of.h [new file with mode: 0644]
drivers/gpu/drm/logicvc/logicvc_regs.h [new file with mode: 0644]