From faa22d48d9929d57975b84ab76cb595afdcf57f4 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Sat, 5 Nov 2022 15:39:47 -0700 Subject: [PATCH] fix(versal-net): add default values for silicon Add missing default value for silicon. Signed-off-by: Michal Simek Change-Id: Iac7d4db17a29a148298e9e3bd3eb3f74cafe7bc1 --- plat/xilinx/versal_net/bl31_versal_net_setup.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/plat/xilinx/versal_net/bl31_versal_net_setup.c b/plat/xilinx/versal_net/bl31_versal_net_setup.c index 97080e91e..c9942d6a5 100644 --- a/plat/xilinx/versal_net/bl31_versal_net_setup.c +++ b/plat/xilinx/versal_net/bl31_versal_net_setup.c @@ -88,6 +88,9 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, uart_clock = 25000000; break; case VERSAL_NET_SILICON: + cpu_clock = 100000000; + uart_clock = 100000000; + break; default: panic(); } -- 2.39.5