From e00fe11df3fee04c7f3137817294d464466dab22 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Tue, 16 Mar 2021 16:42:54 +0800 Subject: [PATCH] fix(imx8m): add ddr4 dvfs sw workaround for ERR050712 APB Write data corruption following MRCTRL0.mr_wr=1 while hardware-driven MR access is occurring When performing a software driven MR access, the following sequence must be done automatically before performing other APB register accesses: 1. Set MRCTRL0.mr_wr=1 2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2) 3. Check for MRSTAT.mr_wr_busy=0 again (for the second time), if not, go to step (2). Signed-off-by: Jacky Bai Reviewed-by: Ye Li Change-Id: Ie26e08bcc83d3ed4844ed04a853162308dcdccd0 --- plat/imx/imx8m/ddr/ddr4_dvfs.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/plat/imx/imx8m/ddr/ddr4_dvfs.c b/plat/imx/imx8m/ddr/ddr4_dvfs.c index d58a0cc1d..94bfaba7e 100644 --- a/plat/imx/imx8m/ddr/ddr4_dvfs.c +++ b/plat/imx/imx8m/ddr/ddr4_dvfs.c @@ -18,9 +18,23 @@ void ddr4_mr_write(uint32_t mr, uint32_t data, uint32_t mr_type, * 1. Poll MRSTAT.mr_wr_busy until it is 0 to make sure * that there is no outstanding MR transAction. */ - while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) { - ; - } + + /* + * ERR050712: + * When performing a software driven MR access, the following sequence + * must be done automatically before performing other APB register accesses. + * 1. Set MRCTRL0.mr_wr=1 + * 2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2) + * 3. Check for MRSTAT.mr_wr_busy=0 again (for the second time). If not, go to step (2) + */ + mmio_setbits_32(DDRC_MRCTRL0(0), BIT(31)); + + do { + while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1) { + ; + } + + } while (mmio_read_32(DDRC_MRSTAT(0)) & 0x1); /* * 2. Write the MRCTRL0.mr_type, MRCTRL0.mr_addr, MRCTRL0.mr_rank -- 2.39.5