From dbb9c1f5b69134ca43c944d84b413331a64fba15 Mon Sep 17 00:00:00 2001 From: Govindraj Raja Date: Wed, 8 Feb 2023 15:04:55 +0000 Subject: [PATCH] feat(fvp): increase BL1_RW and BL2 size To support mbedtls3.3 increase BL1_RW and BL2 size rsa+ecdsa alg. Increase both by one page size. In mbedtls3.3 numerous config options have been tweaked and made defaults[1] thus a small increase in size can result for mbedtls-3.3 This size limitation is observed when we build TF-A with TF_MBEDTLS_KEY_ALG=rsa+ecdsa this approach is used in juno as well, so use similar approach for FVP. [1]: https://github.com/Mbed-TLS/mbedtls/blob/development/docs/3.0-migration-guide.md Change-Id: I8a423711ac50b3d615c1d9650086cdbca5051c8e Signed-off-by: Govindraj Raja --- plat/arm/board/fvp/include/platform_def.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h index 1ef6c87a2..7366cf468 100644 --- a/plat/arm/board/fvp/include/platform_def.h +++ b/plat/arm/board/fvp/include/platform_def.h @@ -16,6 +16,10 @@ #include "../fvp_def.h" +#if TRUSTED_BOARD_BOOT +#include MBEDTLS_CONFIG_FILE +#endif + /* Required platform porting definitions */ #define PLATFORM_CORE_COUNT (U(FVP_CLUSTER_COUNT) * \ U(FVP_MAX_CPUS_PER_CLUSTER) * \ @@ -171,7 +175,11 @@ * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size * plus a little space for growth. */ +#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA +#define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xC000) +#else #define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) +#endif /* * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page @@ -194,7 +202,11 @@ #if TRUSTED_BOARD_BOOT && COT_DESC_IN_DTB # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_BL2_ROMLIB_OPTIMIZATION) #elif CRYPTO_SUPPORT +#if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA +# define PLAT_ARM_MAX_BL2_SIZE (UL(0x1E000) - FVP_BL2_ROMLIB_OPTIMIZATION) +#else # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - FVP_BL2_ROMLIB_OPTIMIZATION) +#endif #elif ARM_BL31_IN_DRAM /* When ARM_BL31_IN_DRAM is set, BL2 can use almost all of Trusted SRAM. */ # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - FVP_BL2_ROMLIB_OPTIMIZATION) -- 2.39.5