From c49879b6a1bbeced56a9384c05b444057aec6050 Mon Sep 17 00:00:00 2001 From: Ben Widawsky Date: Tue, 23 Apr 2013 17:33:02 -0700 Subject: [PATCH] Revert "drm/i915: Don't overclock on Haswell" This reverts commit d395b0446c3eaa429768a79ce8b69042a7fc8419. The latest version of our PM programming doc (which is WAY better than previous versions, and thanks for that) says something along the lines of, "On Haswell overclocking is no long achieved via mailbox registers." Which I misinterpreted as, the driver must done something different than it did on IVB, and SNB. It appears I jumped the gun, and that's all false. We've gotten some clarification, and it appears at least *reading* the overclocking information works in exactly the same manner. Cc: kim.l.saw-chu@intel.com Signed-off-by: Ben Widawsky Signed-off-by: Daniel Vetter --- drivers/gpu/drm/i915/intel_pm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e34ad96425195..de3b0dc5658bc 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2639,7 +2639,7 @@ static void gen6_enable_rps(struct drm_device *dev) (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT)); ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); - if (!ret && (IS_GEN6(dev) || IS_IVYBRIDGE(dev))) { + if (!ret) { pcu_mbox = 0; ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ -- 2.39.5