From bb2289142cbf0f3546c1034e0500b5dc32aef740 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Tue, 21 May 2019 18:59:18 +0200 Subject: [PATCH] feat(debug): add AARCH32 CP15 fault registers For an easier debug on Aarch32, in case of abort, it is useful to access DFSR, IFSR, DFAR and IFAR CP15 registers. Change-Id: Ie6b5a2882cd701f76e9d455ec43bd4b0fbe3cc78 Signed-off-by: Yann Gautier --- include/arch/aarch32/arch.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/include/arch/aarch32/arch.h b/include/arch/aarch32/arch.h index bdff25b4b..8678bf3d8 100644 --- a/include/arch/aarch32/arch.h +++ b/include/arch/aarch32/arch.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -617,6 +617,12 @@ #define ICC_ASGI1R_EL1_64 p15, 1, c12 #define ICC_SGI0R_EL1_64 p15, 2, c12 +/* Fault registers. The format is: coproc, opt1, CRn, CRm, opt2 */ +#define DFSR p15, 0, c5, c0, 0 +#define IFSR p15, 0, c5, c0, 1 +#define DFAR p15, 0, c6, c0, 0 +#define IFAR p15, 0, c6, c0, 2 + /******************************************************************************* * Definitions of MAIR encodings for device and normal memory ******************************************************************************/ -- 2.39.5