From aee2f33a675891f660fc0d06e739ce85f3472075 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 10 Jan 2023 13:14:37 -0600 Subject: [PATCH] feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles The Cortex-A72 based cores on K3 platforms can be clocked fast enough that an extra latency cycle is needed to ensure correct L2 access. Set the latency here for all A72 cores. Signed-off-by: Andrew Davis Change-Id: I639091dd0d2de09572bf0f73ac404e306e336883 --- include/lib/cpus/aarch32/cortex_a72.h | 1 + include/lib/cpus/aarch64/cortex_a72.h | 1 + plat/ti/k3/board/j784s4/board.mk | 4 ++++ plat/ti/k3/common/k3_helpers.S | 10 +++++++++- 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h index 4b1af61ca..c77484026 100644 --- a/include/lib/cpus/aarch32/cortex_a72.h +++ b/include/lib/cpus/aarch32/cortex_a72.h @@ -47,6 +47,7 @@ #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) +#define CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES U(0x3) #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1) #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index 17776458b..a666617f9 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -68,6 +68,7 @@ #define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK U(0x7) #define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK U(0x7) #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) +#define CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES U(0x3) #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1) #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) diff --git a/plat/ti/k3/board/j784s4/board.mk b/plat/ti/k3/board/j784s4/board.mk index 92433ab65..c7fcb0016 100644 --- a/plat/ti/k3/board/j784s4/board.mk +++ b/plat/ti/k3/board/j784s4/board.mk @@ -17,6 +17,10 @@ $(eval $(call add_define,K3_HW_CONFIG_BASE)) K3_SEC_PROXY_LITE := 0 $(eval $(call add_define,K3_SEC_PROXY_LITE)) +# Use a 4 cycle data RAM latency for J784s4 +K3_DATA_RAM_4_LATENCY := 1 +$(eval $(call add_define,K3_DATA_RAM_4_LATENCY)) + # System coherency is managed in hardware USE_COHERENT_MEM := 1 diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/k3/common/k3_helpers.S index f4f7d18ea..cc9934c4e 100644 --- a/plat/ti/k3/common/k3_helpers.S +++ b/plat/ti/k3/common/k3_helpers.S @@ -105,7 +105,15 @@ func plat_reset_handler /* Cortex-A72 specific settings */ a72: mrs x0, CORTEX_A72_L2CTLR_EL1 - orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) +#if K3_DATA_RAM_4_LATENCY + /* Set L2 cache data RAM latency to 4 cycles */ + orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES << \ + CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) +#else + /* Set L2 cache data RAM latency to 3 cycles */ + orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << \ + CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) +#endif msr CORTEX_A72_L2CTLR_EL1, x0 isb ret -- 2.39.5