From a67c1b1b2b521c888790c68e4201ecce0836a0e9 Mon Sep 17 00:00:00 2001 From: Akram Ahmad Date: Fri, 22 Jul 2022 16:20:44 +0100 Subject: [PATCH] fix(errata): workaround for Cortex-A510 erratum 2371937 Cortex-A510 erratum 2371937 is a Cat B erratum that applies to revisions r0p0, r0p1, r0p2, r0p3, r1p0, and r1p1. It is fixed in r1p2. The workaround is to set the ATOM field of CPUECTLR_EL1 (bits [40:38]) to 0b010, which will force all cacheable atomic operations to be executed near. SDEN can be found here: https://developer.arm.com/documentation/SDEN1873351/latest https://developer.arm.com/documentation/SDEN1873361/latest Signed-off-by: Akram Ahmad Change-Id: Ia219a609a3397e39631de65831ecff8a3cd1227e --- docs/design/cpu-specific-build-macros.rst | 4 +++ include/lib/cpus/aarch64/cortex_a510.h | 4 ++- lib/cpus/aarch64/cortex_a510.S | 40 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 +++++ 4 files changed, 55 insertions(+), 1 deletion(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index e15c82e10..e1ca4912c 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -589,6 +589,10 @@ For Cortex-A510, the following errata build flags are defined : Cortex-A510 CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and r1p0, it is fixed in r1p1. +- ``ERRATA_A510_2371937``: This applies errata 2371937 workaround to + Cortex-A510 CPU. This needs to applied for revisions r0p0, r0p1, r0p2, + r0p3, r1p0, r1p1, and is fixed in r1p2. + DSU Errata Workarounds ---------------------- diff --git a/include/lib/cpus/aarch64/cortex_a510.h b/include/lib/cpus/aarch64/cortex_a510.h index 2b8db1420..83bafda12 100644 --- a/include/lib/cpus/aarch64/cortex_a510.h +++ b/include/lib/cpus/aarch64/cortex_a510.h @@ -17,6 +17,8 @@ #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1) #define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23) #define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46) +#define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2) +#define CORTEX_A510_CPUECTLR_EL1_ATOM U(38) /******************************************************************************* * CPU Power Control register specific definitions @@ -34,4 +36,4 @@ ******************************************************************************/ #define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0 -#endif /* CORTEX_A510_H */ +#endif /* CORTEX_A510_H */ \ No newline at end of file diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S index f44407775..da4791a26 100644 --- a/lib/cpus/aarch64/cortex_a510.S +++ b/lib/cpus/aarch64/cortex_a510.S @@ -264,6 +264,40 @@ func check_errata_2172148 b cpu_rev_var_ls endfunc check_errata_2172148 + /*--------------------------------------------------- + * Errata Workaround for Cortex-A510 Errata #2371937. + * This applies to revisions r1p1 and lower, and is + * fixed in r1p2. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0, x1, x17 + *--------------------------------------------------- + */ +func errata_cortex_a510_2371937_wa + mov x17, x30 + bl check_errata_2371937 + cbz x0, 1f + + /* + * Cacheable atomic operations can be forced + * to be executed near by setting + * IMP_CPUECTLR_EL1.ATOM=0b010. ATOM is found + * in [40:38] of CPUECTLR_EL1. + */ + mrs x0, CORTEX_A510_CPUECTLR_EL1 + mov x1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR + bfi x0, x1, CORTEX_A510_CPUECTLR_EL1_ATOM, #3 + msr CORTEX_A510_CPUECTLR_EL1, x0 +1: + ret x17 +endfunc errata_cortex_a510_2371937_wa + +func check_errata_2371937 + /* Applies to r1p1 and lower */ + mov x1, #0x11 + b cpu_rev_var_ls +endfunc check_errata_2371937 + /* ---------------------------------------------------- * HW will do the cache maintenance while powering down * ---------------------------------------------------- @@ -301,6 +335,7 @@ func cortex_a510_errata_report report_errata ERRATA_A510_2250311, cortex_a510, 2250311 report_errata ERRATA_A510_2218950, cortex_a510, 2218950 report_errata ERRATA_A510_2172148, cortex_a510, 2172148 + report_errata ERRATA_A510_2371937, cortex_a510, 2371937 report_errata ERRATA_DSU_2313941, cortex_a510, dsu_2313941 ldp x8, x30, [sp], #16 @@ -352,6 +387,11 @@ func cortex_a510_reset_func bl errata_cortex_a510_2218950_wa #endif +#if ERRATA_A510_2371937 + mov x0, x18 + bl errata_cortex_a510_2371937_wa +#endif + #if ERRATA_A510_2172148 mov x0, x18 bl errata_cortex_a510_2172148_wa diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 3e5e92a95..8964b4107 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -645,6 +645,10 @@ ERRATA_A510_2218950 ?=0 # to revisions r0p0, r0p1, r0p2, r0p3 and r1p0, and is fixed in r1p1. ERRATA_A510_2172148 ?=0 +# Flag to apply erratum 2371937 workaround during reset. This erratum applies +# to revisions r0p0, r0p1, r0p2, r0p3, r1p0, and r1p1. It is fixed in r1p2. +ERRATA_A510_2371937 ?=0 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. ERRATA_DSU_798953 ?=0 @@ -1215,6 +1219,10 @@ $(eval $(call add_define,ERRATA_A510_2218950)) $(eval $(call assert_boolean,ERRATA_A510_2172148)) $(eval $(call add_define,ERRATA_A510_2172148)) +# Process ERRATA_A510_2371937 flag +$(eval $(call assert_boolean,ERRATA_A510_2371937)) +$(eval $(call add_define,ERRATA_A510_2371937)) + # Process ERRATA_DSU_798953 flag $(eval $(call assert_boolean,ERRATA_DSU_798953)) $(eval $(call add_define,ERRATA_DSU_798953)) -- 2.39.5