From a599c80d063975cbeedbc86cfb619fca8545c487 Mon Sep 17 00:00:00 2001 From: Emekcan Aras Date: Wed, 17 Nov 2021 18:45:32 +0000 Subject: [PATCH] feat(corstone1000): implement platform specific psci reset This change implements platform specific psci reset for the corstone1000. Signed-off-by: Emekcan Aras Signed-off-by: Vishnu Banavath Change-Id: I25f77234506416c3376ff4a028f6ea40ebe68437 --- .../corstone1000/common/corstone1000_pm.c | 19 +++++++++++++++++-- .../common/include/platform_def.h | 5 +++++ 2 files changed, 22 insertions(+), 2 deletions(-) diff --git a/plat/arm/board/corstone1000/common/corstone1000_pm.c b/plat/arm/board/corstone1000/common/corstone1000_pm.c index 12b322e27..98dea7963 100644 --- a/plat/arm/board/corstone1000/common/corstone1000_pm.c +++ b/plat/arm/board/corstone1000/common/corstone1000_pm.c @@ -6,17 +6,32 @@ #include #include - +#include /******************************************************************************* * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard * platform layer will take care of registering the handlers with PSCI. ******************************************************************************/ + +static void __dead2 corstone1000_system_reset(void) +{ + + uint32_t volatile * const watchdog_ctrl_reg = (uint32_t *) SECURE_WATCHDOG_ADDR_CTRL_REG; + uint32_t volatile * const watchdog_val_reg = (uint32_t *) SECURE_WATCHDOG_ADDR_VAL_REG; + + *(watchdog_val_reg) = SECURE_WATCHDOG_COUNTDOWN_VAL; + *watchdog_ctrl_reg = SECURE_WATCHDOG_MASK_ENABLE; + while (1) { + wfi(); + } +} + plat_psci_ops_t plat_arm_psci_pm_ops = { - /* dummy struct */ + .system_reset = corstone1000_system_reset, .validate_ns_entrypoint = NULL }; const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) { + ops = &plat_arm_psci_pm_ops; return ops; } diff --git a/plat/arm/board/corstone1000/common/include/platform_def.h b/plat/arm/board/corstone1000/common/include/platform_def.h index 9e4fa0234..acfaf5d01 100644 --- a/plat/arm/board/corstone1000/common/include/platform_def.h +++ b/plat/arm/board/corstone1000/common/include/platform_def.h @@ -272,6 +272,11 @@ #define ARM_SYS_CNTREAD_BASE UL(0x1a210000) #define ARM_SYS_TIMCTL_BASE UL(0x1a220000) +#define SECURE_WATCHDOG_ADDR_CTRL_REG 0x1A320000 +#define SECURE_WATCHDOG_ADDR_VAL_REG 0x1A320008 +#define SECURE_WATCHDOG_MASK_ENABLE 0x01 +#define SECURE_WATCHDOG_COUNTDOWN_VAL 0x1000 + #define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */ #define CORSTONE1000_IRQ_TZ_WDOG 32 -- 2.39.5