From a4e502319d136d8854ef2ed4aaa6d5368541e551 Mon Sep 17 00:00:00 2001 From: Rex-BC Chen Date: Mon, 11 Jul 2022 19:03:35 +0800 Subject: [PATCH] feat(mt8188): add display port control in SiP service MTK display port mute/unmute control registers need to be set in secure world. TEST=build pass BUG=b:236331724 Signed-off-by: Bo-Chen Chen Change-Id: I0aa0675f07c80aab4349493bfbb0782bf0bbef58 --- plat/mediatek/drivers/dp/mt_dp.c | 12 +++++++++++- plat/mediatek/include/mt8188/platform_def.h | 8 ++++++++ plat/mediatek/include/mtk_sip_def.h | 1 + plat/mediatek/mt8188/platform.mk | 1 + 4 files changed, 21 insertions(+), 1 deletion(-) diff --git a/plat/mediatek/drivers/dp/mt_dp.c b/plat/mediatek/drivers/dp/mt_dp.c index 1bf2b444d..8aa246f2b 100644 --- a/plat/mediatek/drivers/dp/mt_dp.c +++ b/plat/mediatek/drivers/dp/mt_dp.c @@ -53,7 +53,7 @@ int32_t dp_secure_handler(uint64_t cmd, uint64_t para, uint32_t *val) if (ret == MTK_SIP_E_SUCCESS) { regmsk = (VIDEO_MUTE_SEL_SECURE_FLDMASK | - VIDEO_MUTE_SW_SECURE_FLDMASK); + VIDEO_MUTE_SW_SECURE_FLDMASK); if (para > 0U) { fldmask = VIDEO_MUTE_SW_SECURE_FLDMASK; } else { @@ -67,3 +67,13 @@ int32_t dp_secure_handler(uint64_t cmd, uint64_t para, uint32_t *val) return ret; } + +u_register_t mtk_dp_sip_handler(u_register_t x1, u_register_t x2, + u_register_t x3, u_register_t x4, + void *handle, struct smccc_res *smccc_ret) +{ + uint32_t ret_val; + + return dp_secure_handler(x1, x2, &ret_val); +} +DECLARE_SMC_HANDLER(MTK_SIP_DP_CONTROL, mtk_dp_sip_handler); diff --git a/plat/mediatek/include/mt8188/platform_def.h b/plat/mediatek/include/mt8188/platform_def.h index 88a9e46e3..15ea5b63a 100644 --- a/plat/mediatek/include/mt8188/platform_def.h +++ b/plat/mediatek/include/mt8188/platform_def.h @@ -41,6 +41,14 @@ #define CIRQ_REG_NUM (23) #define CIRQ_SPI_START (96) +/******************************************************************************* + * DP related constants + ******************************************************************************/ +#define EDP_SEC_BASE (IO_PHYS + 0x0C504000) +#define DP_SEC_BASE (IO_PHYS + 0x0C604000) +#define EDP_SEC_SIZE (0x1000) +#define DP_SEC_SIZE (0x1000) + /******************************************************************************* * System counter frequency related constants ******************************************************************************/ diff --git a/plat/mediatek/include/mtk_sip_def.h b/plat/mediatek/include/mtk_sip_def.h index b591499a5..37734eaa1 100644 --- a/plat/mediatek/include/mtk_sip_def.h +++ b/plat/mediatek/include/mtk_sip_def.h @@ -12,6 +12,7 @@ _func(MTK_SIP_KERNEL_TIME_SYNC, 0x202) \ _func(MTK_SIP_VCORE_CONTROL, 0x506) \ _func(MTK_SIP_APUSYS_CONTROL, 0x51E) \ + _func(MTK_SIP_DP_CONTROL, 0x523) \ _func(MTK_SIP_KERNEL_GIC_OP, 0x526) #define MTK_SIP_SMC_FROM_BL33_TABLE(_func) \ diff --git a/plat/mediatek/mt8188/platform.mk b/plat/mediatek/mt8188/platform.mk index 83a5b95bd..61b61dbe0 100644 --- a/plat/mediatek/mt8188/platform.mk +++ b/plat/mediatek/mt8188/platform.mk @@ -23,6 +23,7 @@ MODULES-y += $(MTK_PLAT)/common MODULES-y += $(MTK_PLAT)/lib/mtk_init MODULES-y += $(MTK_PLAT)/lib/pm MODULES-y += $(MTK_PLAT)/drivers/cirq +MODULES-y += $(MTK_PLAT)/drivers/dp MODULES-y += $(MTK_PLAT)/drivers/gic600 MODULES-y += $(MTK_PLAT)/drivers/timer -- 2.39.5