From 978a824091303748007de308e11af12c2601bc05 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 13 Dec 2020 21:44:54 -0600 Subject: [PATCH] allwinner: Add R_PRCM security setup for H6 H6 has a reorganized R_PRCM compared to A64/H5, with the security switch at a different offset. Until now, we did not notice, because the switch has no effect unless the secure mode e-fuse is blown. Since we are adding more platform-specific CCU registers, move them to their own header, and out of the memory map (where they do not belong). Signed-off-by: Samuel Holland Change-Id: Ie77476db0515080954eaa2e32bf6c3de657cda86 --- plat/allwinner/common/sunxi_security.c | 4 ++-- plat/allwinner/sun50i_a64/include/sunxi_ccu.h | 14 ++++++++++++++ plat/allwinner/sun50i_a64/include/sunxi_mmap.h | 1 - plat/allwinner/sun50i_h6/include/sunxi_ccu.h | 14 ++++++++++++++ plat/allwinner/sun50i_h6/include/sunxi_mmap.h | 1 - 5 files changed, 30 insertions(+), 4 deletions(-) create mode 100644 plat/allwinner/sun50i_a64/include/sunxi_ccu.h create mode 100644 plat/allwinner/sun50i_h6/include/sunxi_ccu.h diff --git a/plat/allwinner/common/sunxi_security.c b/plat/allwinner/common/sunxi_security.c index 92c83b06e..fab3ba81a 100644 --- a/plat/allwinner/common/sunxi_security.c +++ b/plat/allwinner/common/sunxi_security.c @@ -7,6 +7,7 @@ #include #include +#include #include #include @@ -16,7 +17,6 @@ #define SPC_DECPORT_CLR_REG(p) (SUNXI_SPC_BASE + ((p) * 0x0c) + 0xc) #endif -#define R_PRCM_SEC_SWITCH_REG 0x1d0 #define DMA_SEC_REG 0x20 /* @@ -40,7 +40,7 @@ void sunxi_security_setup(void) mmio_write_32(SUNXI_CCU_SEC_SWITCH_REG, 0x7); /* Set R_PRCM bus clocks to non-secure */ - mmio_write_32(SUNXI_R_PRCM_BASE + R_PRCM_SEC_SWITCH_REG, 0x1); + mmio_write_32(SUNXI_R_PRCM_SEC_SWITCH_REG, 0x1); /* Set all DMA channels (16 max.) to non-secure */ mmio_write_32(SUNXI_DMA_BASE + DMA_SEC_REG, 0xffff); diff --git a/plat/allwinner/sun50i_a64/include/sunxi_ccu.h b/plat/allwinner/sun50i_a64/include/sunxi_ccu.h new file mode 100644 index 000000000..2a2488621 --- /dev/null +++ b/plat/allwinner/sun50i_a64/include/sunxi_ccu.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SUNXI_CCU_H +#define SUNXI_CCU_H + +#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0x02f0) + +#define SUNXI_R_PRCM_SEC_SWITCH_REG (SUNXI_R_PRCM_BASE + 0x01d0) + +#endif /* SUNXI_CCU_H */ diff --git a/plat/allwinner/sun50i_a64/include/sunxi_mmap.h b/plat/allwinner/sun50i_a64/include/sunxi_mmap.h index 9d2542fce..6c847d39b 100644 --- a/plat/allwinner/sun50i_a64/include/sunxi_mmap.h +++ b/plat/allwinner/sun50i_a64/include/sunxi_mmap.h @@ -36,7 +36,6 @@ #define SUNXI_MSGBOX_BASE 0x01c17000 #define SUNXI_SPINLOCK_BASE 0x01c18000 #define SUNXI_CCU_BASE 0x01c20000 -#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0x2f0) #define SUNXI_PIO_BASE 0x01c20800 #define SUNXI_TIMER_BASE 0x01c20c00 #define SUNXI_WDOG_BASE 0x01c20ca0 diff --git a/plat/allwinner/sun50i_h6/include/sunxi_ccu.h b/plat/allwinner/sun50i_h6/include/sunxi_ccu.h new file mode 100644 index 000000000..85fbb9080 --- /dev/null +++ b/plat/allwinner/sun50i_h6/include/sunxi_ccu.h @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef SUNXI_CCU_H +#define SUNXI_CCU_H + +#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0x0f00) + +#define SUNXI_R_PRCM_SEC_SWITCH_REG (SUNXI_R_PRCM_BASE + 0x0290) + +#endif /* SUNXI_CCU_H */ diff --git a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h index 702db770f..39a505a81 100644 --- a/plat/allwinner/sun50i_h6/include/sunxi_mmap.h +++ b/plat/allwinner/sun50i_h6/include/sunxi_mmap.h @@ -30,7 +30,6 @@ #define SUNXI_DMA_BASE 0x03002000 #define SUNXI_MSGBOX_BASE 0x03003000 #define SUNXI_CCU_BASE 0x03001000 -#define SUNXI_CCU_SEC_SWITCH_REG (SUNXI_CCU_BASE + 0xf00) #define SUNXI_PIO_BASE 0x0300b000 #define SUNXI_TIMER_BASE 0x03009000 #define SUNXI_WDOG_BASE 0x030090a0 -- 2.39.5