From 8e53b2fa2eef44457ae1b50cd116e13d67df35f8 Mon Sep 17 00:00:00 2001 From: Sieu Mun Tang Date: Fri, 1 Jul 2022 09:08:57 +0800 Subject: [PATCH] fix(intel): fix UART baud rate and clock Revise the UART baud rate and clock for general platform build, SIMIC build and EMU build. Signed-off-by: Sieu Mun Tang Change-Id: I62fefe7b96d5124e75d2810b4fbc1640422b1353 --- plat/intel/soc/agilex/platform.mk | 1 - plat/intel/soc/common/include/platform_def.h | 11 +++++------ plat/intel/soc/n5x/platform.mk | 1 - plat/intel/soc/stratix10/platform.mk | 1 - 4 files changed, 5 insertions(+), 9 deletions(-) diff --git a/plat/intel/soc/agilex/platform.mk b/plat/intel/soc/agilex/platform.mk index ccb4e071f..a1e58fcca 100644 --- a/plat/intel/soc/agilex/platform.mk +++ b/plat/intel/soc/agilex/platform.mk @@ -80,5 +80,4 @@ PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 BL2_INV_DCACHE := 0 MULTI_CONSOLE_API := 1 -SIMICS_BUILD := 0 USE_COHERENT_MEM := 1 diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h index a31adf707..2b3f144ca 100644 --- a/plat/intel/soc/common/include/platform_def.h +++ b/plat/intel/soc/common/include/platform_def.h @@ -17,6 +17,7 @@ #define PLAT_SOCFPGA_STRATIX10 1 #define PLAT_SOCFPGA_AGILEX 2 #define PLAT_SOCFPGA_N5X 3 +#define PLAT_SOCFPGA_EMULATOR 0 /* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */ #define PLAT_CPU_RELEASE_ADDR 0xffd12210 @@ -170,14 +171,12 @@ #define CRASH_CONSOLE_BASE PLAT_UART0_BASE #define PLAT_INTEL_UART_BASE PLAT_UART0_BASE -#ifndef SIMICS_BUILD -#define PLAT_BAUDRATE (115200) -#define PLAT_UART_CLOCK (100000000) - -#else +#if PLAT_SOCFPGA_EMULATOR #define PLAT_BAUDRATE (4800) #define PLAT_UART_CLOCK (76800) - +#else +#define PLAT_BAUDRATE (115200) +#define PLAT_UART_CLOCK (100000000) #endif /******************************************************************************* diff --git a/plat/intel/soc/n5x/platform.mk b/plat/intel/soc/n5x/platform.mk index 953bf0caf..be1ad8c6b 100644 --- a/plat/intel/soc/n5x/platform.mk +++ b/plat/intel/soc/n5x/platform.mk @@ -49,5 +49,4 @@ PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 BL2_INV_DCACHE := 0 MULTI_CONSOLE_API := 1 -SIMICS_BUILD := 0 USE_COHERENT_MEM := 1 diff --git a/plat/intel/soc/stratix10/platform.mk b/plat/intel/soc/stratix10/platform.mk index 5c0b42146..b7eb4bd77 100644 --- a/plat/intel/soc/stratix10/platform.mk +++ b/plat/intel/soc/stratix10/platform.mk @@ -77,5 +77,4 @@ BL31_SOURCES += \ PROGRAMMABLE_RESET_ADDRESS := 0 BL2_AT_EL3 := 1 -SIMICS_BUILD := 0 USE_COHERENT_MEM := 1 -- 2.39.5