From 8962bdd603508f649fd7a332e580c0e456ccc0ad Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Tue, 14 Jan 2020 14:19:05 +0800 Subject: [PATCH] feat(imx8mq): enable dram dvfs support on imx8mq Enable DRAM DVFS support on i.MX8MQ. Signed-off-by: Jacky Bai Change-Id: Id72c5eb9625936052ec51e5a52d9d31175ed1b1b --- plat/imx/common/imx_sip_svc.c | 2 ++ plat/imx/common/include/imx_sip_svc.h | 2 ++ plat/imx/imx8m/ddr/clock.c | 2 +- plat/imx/imx8m/ddr/dram.c | 9 ++++++++- plat/imx/imx8m/include/gpc.h | 1 + 5 files changed, 14 insertions(+), 2 deletions(-) diff --git a/plat/imx/common/imx_sip_svc.c b/plat/imx/common/imx_sip_svc.c index a816c8073..6d6633cfc 100644 --- a/plat/imx/common/imx_sip_svc.c +++ b/plat/imx/common/imx_sip_svc.c @@ -36,6 +36,8 @@ static uintptr_t imx_sip_handler(unsigned int smc_fid, case IMX_SIP_GPC: SMC_RET1(handle, imx_gpc_handler(smc_fid, x1, x2, x3)); break; + case IMX_SIP_DDR_DVFS: + return dram_dvfs_handler(smc_fid, handle, x1, x2, x3); #endif #if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp) case IMX_SIP_DDR_DVFS: diff --git a/plat/imx/common/include/imx_sip_svc.h b/plat/imx/common/include/imx_sip_svc.h index 1c319e8d8..0e91c7174 100644 --- a/plat/imx/common/include/imx_sip_svc.h +++ b/plat/imx/common/include/imx_sip_svc.h @@ -57,6 +57,8 @@ int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3); int imx_gpc_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2, u_register_t x3); +int dram_dvfs_handler(uint32_t smc_fid, void *handle, + u_register_t x1, u_register_t x2, u_register_t x3); #endif #if defined(PLAT_imx8mm) || defined(PLAT_imx8mn) || defined(PLAT_imx8mp) int dram_dvfs_handler(uint32_t smc_fid, void *handle, diff --git a/plat/imx/imx8m/ddr/clock.c b/plat/imx/imx8m/ddr/clock.c index 986ba6139..8b132d231 100644 --- a/plat/imx/imx8m/ddr/clock.c +++ b/plat/imx/imx8m/ddr/clock.c @@ -76,7 +76,7 @@ void dram_pll_init(unsigned int drate) /* unbypass the PLL */ mmio_clrbits_32(HW_DRAM_PLL_CFG0, 0x30); - while (!(mmio_read_32(HW_DRAM_PLL_CFG0) & (1 << 31))) { + while (!(mmio_read_32(HW_DRAM_PLL_CFG0) & BIT(31))) { ; } } diff --git a/plat/imx/imx8m/ddr/dram.c b/plat/imx/imx8m/ddr/dram.c index f5f9df7a4..b5f697334 100644 --- a/plat/imx/imx8m/ddr/dram.c +++ b/plat/imx/imx8m/ddr/dram.c @@ -11,6 +11,7 @@ #include #include +#include #define IMX_SIP_DDR_DVFS_GET_FREQ_COUNT 0x10 #define IMX_SIP_DDR_DVFS_GET_FREQ_INFO 0x11 @@ -350,7 +351,13 @@ int dram_dvfs_handler(uint32_t smc_fid, void *handle, plat_ic_raise_el3_sgi(0x8, i); } } - +#if defined(PLAT_imx8mq) + for (unsigned int i = 0; i < PLATFORM_CORE_COUNT; i++) { + if (i != cpu_id && online_cores & (1 << (i * 8))) { + imx_gpc_core_wake(1 << i); + } + } +#endif /* make sure all the core in WFE */ online_cores &= ~(0x1 << (cpu_id * 8)); while (1) { diff --git a/plat/imx/imx8m/include/gpc.h b/plat/imx/imx8m/include/gpc.h index eb33abd6c..8eb3e06bc 100644 --- a/plat/imx/imx8m/include/gpc.h +++ b/plat/imx/imx8m/include/gpc.h @@ -80,6 +80,7 @@ void imx_gpc_pm_domain_enable(uint32_t domain_id, bool on); #if defined(PLAT_imx8mq) void imx_gpc_set_a53_core_awake(uint32_t core_id); +void imx_gpc_core_wake(uint32_t cpumask); #endif #endif /*IMX8M_GPC_H */ -- 2.39.5