From 81858a353f8e45f5cc57ce855188043b1745ea08 Mon Sep 17 00:00:00 2001 From: Andrew Davis Date: Tue, 10 Jan 2023 13:25:42 -0600 Subject: [PATCH] feat(ti): set L2 cache ECC and and parity on A72 cores The Cortex-A72 based cores on K3 platforms have cache ECC and parity protection, enable these. Signed-off-by: Andrew Davis Change-Id: Icd00bc4aa9c1c48f0fb2a10ea66e75e0b146ef3c --- include/lib/cpus/aarch32/cortex_a72.h | 3 +++ include/lib/cpus/aarch64/cortex_a72.h | 3 +++ plat/ti/k3/common/k3_helpers.S | 3 +++ 3 files changed, 9 insertions(+) diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h index c77484026..3fbc46531 100644 --- a/include/lib/cpus/aarch32/cortex_a72.h +++ b/include/lib/cpus/aarch32/cortex_a72.h @@ -43,6 +43,9 @@ ******************************************************************************/ #define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2 +#define CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE (ULL(1) << 21) +#define CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE (ULL(1) << 20) + #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index a666617f9..f592fdcd0 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -60,6 +60,9 @@ ******************************************************************************/ #define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 +#define CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE (ULL(1) << 21) +#define CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE (ULL(1) << 20) + #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) #define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT U(5) #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/k3/common/k3_helpers.S index cc9934c4e..6742e74f1 100644 --- a/plat/ti/k3/common/k3_helpers.S +++ b/plat/ti/k3/common/k3_helpers.S @@ -114,6 +114,9 @@ a72: orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << \ CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) #endif + /* Enable L2 ECC and parity with inline data */ + orr x0, x0, #CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE + orr x0, x0, #CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE msr CORTEX_A72_L2CTLR_EL1, x0 isb ret -- 2.39.5