From 7e491133fcf8368a6ff202197f6fd81ac320538d Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Mon, 22 Apr 2019 16:12:30 -0700 Subject: [PATCH] Tegra194: memctrl: update TZDRAM base at 1MB granularity The Memory controller expects the TZDRAM base value at 1MB granularity and the current driver does not respect that limitation. This patch fixes that anomaly. Change-Id: I6b72270f331ba5081e19811df4a78623e457341a Signed-off-by: Varun Wadekar --- plat/nvidia/tegra/soc/t194/plat_memctrl.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c index 9a4d22e68..078c72ab9 100644 --- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c +++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c @@ -447,6 +447,8 @@ tegra_mc_settings_t *tegra_get_mc_settings(void) void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) { uint32_t sec_reg_ctrl = tegra_mc_read_32(MC_SECURITY_CFG_REG_CTRL_0); + uint32_t phys_base_lo = (uint32_t)phys_base & 0xFFF00000; + uint32_t phys_base_hi = (uint32_t)(phys_base >> 32); /* * Check TZDRAM carveout register access status. Setup TZDRAM fence @@ -461,8 +463,8 @@ void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes) */ INFO("Configuring TrustZone DRAM Memory Carveout\n"); - tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base); - tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32)); + tegra_mc_write_32(MC_SECURITY_CFG0_0, phys_base_lo); + tegra_mc_write_32(MC_SECURITY_CFG3_0, phys_base_hi); tegra_mc_write_32(MC_SECURITY_CFG1_0, (uint32_t)(size_in_bytes >> 20)); /* -- 2.39.5