From 7e3f6a87d74efec780c0832c0535dd64ef830cfa Mon Sep 17 00:00:00 2001 From: Arunachalam Ganapathy Date: Mon, 11 Apr 2022 17:38:17 +0100 Subject: [PATCH] fix(plat/tc): increase TC_TZC_DRAM1_SIZE Increase TC_TZC_DRAM1_SIZE for Trusty image and its memory size. Update OP-TEE reserved memory range in DTS Change-Id: Iad433c3c155f28860b15bde2398df653487189dd Signed-off-by: Arunachalam Ganapathy Signed-off-by: Davidson K --- fdts/tc.dts | 4 ++-- plat/arm/board/tc/include/platform_def.h | 29 +++++++++++++++++++----- 2 files changed, 25 insertions(+), 8 deletions(-) diff --git a/fdts/tc.dts b/fdts/tc.dts index fdde0153f..192f407c3 100644 --- a/fdts/tc.dts +++ b/fdts/tc.dts @@ -213,9 +213,9 @@ linux,cma-default; }; - optee@0xfce00000 { + optee@0xf8e00000 { compatible = "restricted-dma-pool"; - reg = <0x00000000 0xfce00000 0 0x00200000>; + reg = <0x00000000 0xf8e00000 0 0x00200000>; }; }; diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h index 0fe4a0a77..a3b7839eb 100644 --- a/plat/arm/board/tc/include/platform_def.h +++ b/plat/arm/board/tc/include/platform_def.h @@ -25,13 +25,28 @@ * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC, * its base is ARM_AP_TZC_DRAM1_BASE. * - * Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for: + * Reserve 96 MB below ARM_AP_TZC_DRAM1_BASE for: * - BL32_BASE when SPD_spmd is enabled - * - Region to load Trusted OS + * - Region to load secure partitions + * + * + * 0xF900_0000 ------------------ TC_TZC_DRAM1_BASE + * | | + * | SPMC | + * | SP | + * | (96MB) | + * 0xFF00_0000 ------------------ ARM_AP_TZC_DRAM1_BASE + * | AP | + * | EL3 Monitor | + * | SCP | + * | (16MB) | + * 0xFFFF_FFFF ------------------ + * + * */ #define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ TC_TZC_DRAM1_SIZE) -#define TC_TZC_DRAM1_SIZE UL(0x02000000) /* 32 MB */ +#define TC_TZC_DRAM1_SIZE 96 * SZ_1M /* 96 MB */ #define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \ TC_TZC_DRAM1_SIZE - 1) @@ -68,7 +83,9 @@ * max size of BL32 image. */ #if defined(SPD_spmd) -#define PLAT_ARM_SPMC_BASE TC_TZC_DRAM1_BASE +#define TC_EL2SPMC_LOAD_ADDR (TC_TZC_DRAM1_BASE + 0x04000000) + +#define PLAT_ARM_SPMC_BASE TC_EL2SPMC_LOAD_ADDR #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ #endif @@ -276,8 +293,8 @@ (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT)) /* - * The first region below, TC_TZC_DRAM1_BASE (0xfd000000) to - * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 48 MB of DRAM as + * The first region below, TC_TZC_DRAM1_BASE (0xf9000000) to + * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 112 MB of DRAM as * secure. The second and third regions gives non secure access to rest of DRAM. */ #define TC_TZC_REGIONS_DEF \ -- 2.39.5