From 7d1700c4d475358539c9a84cb325183c86a06f33 Mon Sep 17 00:00:00 2001 From: Sona Mathew Date: Wed, 11 Jan 2023 12:55:30 -0600 Subject: [PATCH] fix(cpus): workaround for Cortex-A78 erratum 2779479 Cortex-A78 erratum 2779479 is a Cat B erratum that applies to all revisions <= r1p2 and is still open. The workaround is to set the CPUACTLR3_EL1[47] bit to 1. Setting this bit might have a small impact on power and negligible impact on performance. SDEN documentation: https://developer.arm.com/documentation/SDEN1401784/latest Change-Id: I3779fd1eff3017c5961ffa101b357918070b3b36 Signed-off-by: Sona Mathew --- docs/design/cpu-specific-build-macros.rst | 4 +++ include/lib/cpus/aarch64/cortex_a78.h | 4 ++- lib/cpus/aarch64/cortex_a78.S | 37 ++++++++++++++++++++++- lib/cpus/cpu-ops.mk | 8 +++++ 4 files changed, 51 insertions(+), 2 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 8a8445db4..4ae4e544c 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -321,6 +321,10 @@ For Cortex-A78, the following errata build flags are defined : CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1, and r1p2, and it is still open. +- ``ERRATA_A78_2779479``: This applies erratum 2779479 workaround to Cortex-A78 + CPU. This needs to be enabled for revisions r0p0, r1p0, r1p1 and r1p2 and + it is still open. + For Cortex-A78 AE, the following errata build flags are defined : - ``ERRATA_A78_AE_1941500`` : This applies errata 1941500 workaround to diff --git a/include/lib/cpus/aarch64/cortex_a78.h b/include/lib/cpus/aarch64/cortex_a78.h index 31da99e11..fb325b6d7 100644 --- a/include/lib/cpus/aarch64/cortex_a78.h +++ b/include/lib/cpus/aarch64/cortex_a78.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, ARM Limited. All rights reserved. + * Copyright (c) 2019-2023, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -40,6 +40,8 @@ #define CORTEX_A78_ACTLR2_EL1_BIT_2 (ULL(1) << 2) #define CORTEX_A78_ACTLR2_EL1_BIT_40 (ULL(1) << 40) +#define CORTEX_A78_ACTLR3_EL1 S3_0_C15_C1_2 + /******************************************************************************* * CPU Activity Monitor Unit register specific definitions. ******************************************************************************/ diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S index 38f58bb98..a3932e8fc 100644 --- a/lib/cpus/aarch64/cortex_a78.S +++ b/lib/cpus/aarch64/cortex_a78.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2022, ARM Limited. All rights reserved. + * Copyright (c) 2019-2023, ARM Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -351,6 +351,35 @@ func check_errata_2772019 b cpu_rev_var_ls endfunc check_errata_2772019 +/* ---------------------------------------------------- + * Errata Workaround for Cortex A78 Errata 2779479. + * This applies to revisions r0p0, r1p0, r1p1, and r1p2. + * It is still open. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x1, x17 + * ---------------------------------------------------- + */ +func errata_a78_2779479_wa + /* Check revision. */ + mov x17, x30 + bl check_errata_2779479 + cbz x0, 1f + + /* Apply the workaround */ + mrs x1, CORTEX_A78_ACTLR3_EL1 + orr x1, x1, #BIT(47) + msr CORTEX_A78_ACTLR3_EL1, x1 + +1: + ret x17 +endfunc errata_a78_2779479_wa + +func check_errata_2779479 + /* Applies to r0p0, r1p0, r1p1, r1p2 */ + mov x1, #CPU_REV(1, 2) + b cpu_rev_var_ls +endfunc check_errata_2779479 + func check_errata_cve_2022_23960 #if WORKAROUND_CVE_2022_23960 mov x0, #ERRATA_APPLIES @@ -414,6 +443,11 @@ func cortex_a78_reset_func bl errata_a78_2395406_wa #endif +#if ERRATA_A78_2779479 + mov x0, x18 + bl errata_a78_2779479_wa +#endif + #if ENABLE_AMU /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ mrs x0, actlr_el3 @@ -493,6 +527,7 @@ func cortex_a78_errata_report report_errata ERRATA_A78_2376745, cortex_a78, 2376745 report_errata ERRATA_A78_2395406, cortex_a78, 2395406 report_errata ERRATA_A78_2772019, cortex_a78, 2772019 + report_errata ERRATA_A78_2779479, cortex_a78, 2779479 report_errata WORKAROUND_CVE_2022_23960, cortex_a78, cve_2022_23960 ldp x8, x30, [sp], #16 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index c9b444797..ae6baa717 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -362,6 +362,10 @@ ERRATA_A78_2395406 ?=0 # open. ERRATA_A78_2772019 ?=0 +# Flag to apply erratum 2779479 workaround during reset. This erratum applies +# to revision r0p0, r1p0, r1p1 and r1p2 of the A78 cpu. It is still open. +ERRATA_A78_2779479 ?=0 + # Flag to apply erratum 1941500 workaround during reset. This erratum applies # to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open. ERRATA_A78_AE_1941500 ?=0 @@ -1030,6 +1034,10 @@ $(eval $(call add_define,ERRATA_A78_2395406)) $(eval $(call assert_boolean,ERRATA_A78_2772019)) $(eval $(call add_define,ERRATA_A78_2772019)) +# Process ERRATA_A78_2779479 flag +$(eval $(call assert_boolean,ERRATA_A78_2779479)) +$(eval $(call add_define,ERRATA_A78_2779479)) + # Process ERRATA_A78_AE_1941500 flag $(eval $(call assert_boolean,ERRATA_A78_AE_1941500)) $(eval $(call add_define,ERRATA_A78_AE_1941500)) -- 2.39.5