From 7a181b7d046a710db5238fb37047816636d2bb8a Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 23 Mar 2023 11:50:32 +0000 Subject: [PATCH] fix(cpus): use hint instruction for "tsb csync" The "tsb csync" instruction is part of the Armv8.4 architecture extension, and is not supported by many older assemblers. We already cater for this in lib/extensions/trbe/trbe.c, where we use the equivalent "hint #18" encoding for this, but use the new mnemonic in the Cortex-A510 CPU support code. Replace "tsb csync" with the hint encoding there as well, to support building with older binutils versions. Change-Id: Idf39f5c6c4dbf72802c3c120047b8bc499145e3b Signed-off-by: Andre Przywara --- lib/cpus/aarch64/cortex_a510.S | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S index 886e1f3c8..e10ebb0b8 100644 --- a/lib/cpus/aarch64/cortex_a510.S +++ b/lib/cpus/aarch64/cortex_a510.S @@ -382,7 +382,11 @@ func errata_cortex_a510_2684597_wa bl check_errata_2684597 cbz x0, 2f - tsb csync + /* + * Many assemblers do not yet understand the "tsb csync" mnemonic, + * so use the equivalent hint instruction. + */ + hint #18 /* tsb csync */ 2: ret x17 endfunc errata_cortex_a510_2684597_wa -- 2.39.5