From 777d37a807dad98d14b6c12b8397a76ddf2b627b Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Sat, 26 Jun 2021 00:47:22 +0530 Subject: [PATCH] mtd: spi-nor-core: Do not make invalid quad enable fatal The Micron MT35XU512ABA flash does not support the quad enable bit. But instead of programming the Quad Enable Require field to 000b ("Device does not have a QE bit"), it is programmed to 111b ("Reserved"). While this is technically incorrect, it is not reason enough to abort BFPT parsing. Instead, continue BFPT parsing assuming there is no quad enable bit present. Signed-off-by: Pratyush Yadav Reviewed-by: Jagan Teki --- drivers/mtd/spi/spi-nor-core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index cdb464813b..b5b1ac8b5b 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -2100,7 +2100,8 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, break; #endif default: - return -EINVAL; + dev_dbg(nor->dev, "BFPT QER reserved value used\n"); + break; } /* Stop here if JESD216 rev B. */ -- 2.39.5