From 7126b4ea19b65df7d4380fa58c54aa8c7ad3ef9c Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Wed, 24 Jun 2020 06:41:17 -0400 Subject: [PATCH] riscv: Clear pending interrupts before enabling IPIs On some platforms (k210), the previous stage bootloader may have not cleared pending IPIs before transferring control to U-Boot. This can cause race conditions, as multiple harts all attempt to initialize the IPI controller at once. This patch clears IPIs before enabling them, ensuring that only one hart modifies shared memory at once. Signed-off-by: Sean Anderson Reviewed-by: Rick Chen --- arch/riscv/cpu/start.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 5f1c220e0c..f408e41ab9 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -65,6 +65,8 @@ _start: #else li t0, SIE_SSIE #endif + /* Clear any pending IPIs */ + csrc MODE_PREFIX(ip), t0 csrs MODE_PREFIX(ie), t0 #endif -- 2.39.5