From 6beca480fe683d0840f1bad1d8ad15d95a28dda8 Mon Sep 17 00:00:00 2001 From: Steffen Trumtrar Date: Wed, 27 Mar 2013 23:07:06 +0000 Subject: [PATCH] net/macb: force endian_swp_pkt_en to off The core has a bit for swapping packet data endianism. Reset default from Cadence is off. Xilinx however, who uses this core on the Zynq SoCs, opted for on. Force it to off. This shouldn't change the behaviour for current users of the macb, but enables usage on Zynq devices. Signed-off-by: Steffen Trumtrar Cc: Nicolas Ferre Signed-off-by: David S. Miller --- drivers/net/ethernet/cadence/macb.c | 1 + drivers/net/ethernet/cadence/macb.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/net/ethernet/cadence/macb.c b/drivers/net/ethernet/cadence/macb.c index 3593c2c594a64..2747a7f595285 100644 --- a/drivers/net/ethernet/cadence/macb.c +++ b/drivers/net/ethernet/cadence/macb.c @@ -1057,6 +1057,7 @@ static void macb_configure_dma(struct macb *bp) dmacfg |= GEM_BF(RXBS, RX_BUFFER_SIZE / 64); dmacfg |= GEM_BF(FBLDO, 16); dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L); + dmacfg &= ~GEM_BIT(ENDIA); gem_writel(bp, DMACFG, dmacfg); } } diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 570908b935784..993d703806885 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -173,6 +173,8 @@ /* Bitfields in DMACFG. */ #define GEM_FBLDO_OFFSET 0 #define GEM_FBLDO_SIZE 5 +#define GEM_ENDIA_OFFSET 7 +#define GEM_ENDIA_SIZE 1 #define GEM_RXBMS_OFFSET 8 #define GEM_RXBMS_SIZE 2 #define GEM_TXPBMS_OFFSET 10 -- 2.39.5