From 6979f47fecfd34ac1405117c23f2e36ecb552a20 Mon Sep 17 00:00:00 2001 From: Bipin Ravi Date: Fri, 15 Jul 2022 17:20:16 -0500 Subject: [PATCH] fix(errata): workaround for Cortex A78C erratum 2242638 Cortex A78C erratum 2242638 is a Cat B erratum which applies to revisions r0p1, r0p2 and is still open. The workaround is to apply a CPU implementation specific specific patch sequence. SDEN can be found here: https://developer.arm.com/documentation/SDEN2004089/latest Signed-off-by: Bipin Ravi Change-Id: I35d385245a04a39b87be71c1a42312f75e1152e5 --- docs/design/cpu-specific-build-macros.rst | 4 +++ include/lib/cpus/aarch64/cortex_a78c.h | 8 +++++ lib/cpus/aarch64/cortex_a78c.S | 41 +++++++++++++++++++++++ lib/cpus/cpu-ops.mk | 8 +++++ 4 files changed, 61 insertions(+) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 2e3fe74a9..b05364709 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -331,6 +331,10 @@ For Cortex-A78C, the following errata build flags are defined : Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and it is still open. +- ``ERRATA_A78C_2242638`` : This applies errata 2242638 workaround to + Cortex-A78C CPU. This needs to be enabled for revisions r0p1, r0p2 and + it is still open. + For Cortex-X1 CPU, the following errata build flags are defined: - ``ERRATA_X1_1821534`` : This applies errata 1821534 workaround to Cortex-X1 diff --git a/include/lib/cpus/aarch64/cortex_a78c.h b/include/lib/cpus/aarch64/cortex_a78c.h index 39e2adf89..54c95ad2d 100644 --- a/include/lib/cpus/aarch64/cortex_a78c.h +++ b/include/lib/cpus/aarch64/cortex_a78c.h @@ -26,4 +26,12 @@ #define CORTEX_A78C_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) +/******************************************************************************* + * CPU Implementation Specific Selected Instruction registers + ******************************************************************************/ +#define CORTEX_A78C_IMP_CPUPSELR_EL3 S3_6_C15_C8_0 +#define CORTEX_A78C_IMP_CPUPCR_EL3 S3_6_C15_C8_1 +#define CORTEX_A78C_IMP_CPUPOR_EL3 S3_6_C15_C8_2 +#define CORTEX_A78C_IMP_CPUPMR_EL3 S3_6_C15_C8_3 + #endif /* CORTEX_A78C_H */ diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S index f57ecaf8c..fc002e9be 100644 --- a/lib/cpus/aarch64/cortex_a78c.S +++ b/lib/cpus/aarch64/cortex_a78c.S @@ -58,6 +58,41 @@ func check_errata_2132064 b cpu_rev_var_range endfunc check_errata_2132064 +/* -------------------------------------------------------------------- + * Errata Workaround for A78C Erratum 2242638. + * This applies to revisions r0p1 and r0p2 of the Cortex A78C + * processor and is still open. + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: x0-x17 + * -------------------------------------------------------------------- + */ +func errata_a78c_2242638_wa + /* Compare x0 against revisions r0p1 - r0p2 */ + mov x17, x30 + bl check_errata_2242638 + cbz x0, 1f + + ldr x0, =0x5 + msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0 + ldr x0, =0x10F600E000 + msr CORTEX_A78C_IMP_CPUPOR_EL3, x0 + ldr x0, =0x10FF80E000 + msr CORTEX_A78C_IMP_CPUPMR_EL3, x0 + ldr x0, =0x80000000003FF + msr CORTEX_A78C_IMP_CPUPCR_EL3, x0 + + isb +1: + ret x17 +endfunc errata_a78c_2242638_wa + +func check_errata_2242638 + /* Applies to revisions r0p1-r0p2. */ + mov x1, #CPU_REV(0, 1) + mov x2, #CPU_REV(0, 2) + b cpu_rev_var_range +endfunc check_errata_2242638 + func check_errata_cve_2022_23960 #if WORKAROUND_CVE_2022_23960 mov x0, #ERRATA_APPLIES @@ -81,6 +116,11 @@ func cortex_a78c_reset_func bl errata_a78c_2132064_wa #endif +#if ERRATA_A78C_2242638 + mov x0, x18 + bl errata_a78c_2242638_wa +#endif + #if IMAGE_BL31 && WORKAROUND_CVE_2022_23960 /* * The Cortex-A78c generic vectors are overridden to apply errata @@ -125,6 +165,7 @@ func cortex_a78c_errata_report * checking functions of each errata. */ report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064 + report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638 report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960 ldp x8, x30, [sp], #16 diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 19e611c60..2c08a27b8 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -365,6 +365,10 @@ ERRATA_A78_AE_2395408 ?=0 # to revisions r0p1 and r0p2 of the A78C cpu. It is still open. ERRATA_A78C_2132064 ?=0 +# Flag to apply erratum 2242638 workaround during reset. This erratum applies +# to revisions r0p1 and r0p2 of the A78C cpu. It is still open. +ERRATA_A78C_2242638 ?=0 + # Flag to apply erratum 1821534 workaround during reset. This erratum applies # to revisions r0p0 - r1p0 of the X1 cpu and fixed in r1p1. ERRATA_X1_1821534 ?=0 @@ -923,6 +927,10 @@ $(eval $(call add_define,ERRATA_A78_AE_2395408)) $(eval $(call assert_boolean,ERRATA_A78C_2132064)) $(eval $(call add_define,ERRATA_A78C_2132064)) +# Process ERRATA_A78C_2242638 flag +$(eval $(call assert_boolean,ERRATA_A78C_2242638)) +$(eval $(call add_define,ERRATA_A78C_2242638)) + # Process ERRATA_X1_1821534 flag $(eval $(call assert_boolean,ERRATA_X1_1821534)) $(eval $(call add_define,ERRATA_X1_1821534)) -- 2.39.5