From 5f0f7e47e05f98587d424c2162d1ce20af4f588d Mon Sep 17 00:00:00 2001 From: Jay Buddhabhatti Date: Thu, 29 Dec 2022 22:15:19 -0800 Subject: [PATCH] fix(versal-net): clear power down bit during wakeup Power down bit and power down interrupt needs to be cleared once core is wakeup to avoid unnecessary power down events. So disable power down interrupt and clear power down bit during client wakeup. Signed-off-by: Jay Buddhabhatti Change-Id: I3445991692c441831e4ea8dae112e23b19f185a9 --- plat/xilinx/versal_net/pm_service/pm_client.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/plat/xilinx/versal_net/pm_service/pm_client.c b/plat/xilinx/versal_net/pm_service/pm_client.c index b7c6db5a3..0142f3358 100644 --- a/plat/xilinx/versal_net/pm_service/pm_client.c +++ b/plat/xilinx/versal_net/pm_service/pm_client.c @@ -201,6 +201,7 @@ static uint32_t pm_get_cpuid(uint32_t nid) void pm_client_wakeup(const struct pm_proc *proc) { uint32_t cpuid = pm_get_cpuid(proc->node_id); + uintptr_t val; if (cpuid == UNDEFINED_CPUID) { return; @@ -208,7 +209,16 @@ void pm_client_wakeup(const struct pm_proc *proc) bakery_lock_get(&pm_client_secure_lock); - /* TODO: clear powerdown bit for affected cpu */ + /* Clear powerdown request */ + val = read_cpu_pwrctrl_val(); + val &= ~CORE_PWRDN_EN_BIT_MASK; + write_cpu_pwrctrl_val(val); + + isb(); + + /* Disabled power down interrupt */ + mmio_write_32(APU_PCIL_CORE_X_IDS_POWER_REG(cpuid), + APU_PCIL_CORE_X_IDS_POWER_MASK); bakery_lock_release(&pm_client_secure_lock); } -- 2.39.5