From 5d68e8913ea983b21eb4a1163e6215ff8f8e96e4 Mon Sep 17 00:00:00 2001 From: Sylwester Garncarek Date: Sat, 7 Jan 2023 08:50:25 +0700 Subject: [PATCH] fix(gicv3): fixed bug in the initialization of GICv3 SGIs/(E)PPIs interrupt priorities Default priority was not being set for all interrupts (gicr_write_ipriorityr takes INTID, not register number). The fix makes the loop to pass INTID in range 0, 4, 8, 12, ... Signed-off-by: Sylwester Garncarek Change-Id: Iaa975f6af49f5826c2811161f55242844c28ea81 --- drivers/arm/gic/v3/gicv3_helpers.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/arm/gic/v3/gicv3_helpers.c b/drivers/arm/gic/v3/gicv3_helpers.c index 446d0addb..940c939af 100644 --- a/drivers/arm/gic/v3/gicv3_helpers.c +++ b/drivers/arm/gic/v3/gicv3_helpers.c @@ -253,7 +253,7 @@ unsigned int gicv3_secure_spis_config_props(uintptr_t gicd_base, } /******************************************************************************* - * Helper function to configure the default attributes of (E)SPIs + * Helper function to configure the default attributes of (E)PPIs/SGIs ******************************************************************************/ void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base) { @@ -292,7 +292,7 @@ void gicv3_ppi_sgi_config_defaults(uintptr_t gicr_base) regs_num = ppi_regs_num << 3; for (i = 0U; i < regs_num; ++i) { /* Setup the default (E)PPI/SGI priorities doing 4 at a time */ - gicr_write_ipriorityr(gicr_base, i, GICD_IPRIORITYR_DEF_VAL); + gicr_write_ipriorityr(gicr_base, i << 2, GICD_IPRIORITYR_DEF_VAL); } /* 16 interrupt IDs per GICR_ICFGR register */ -- 2.39.5