From 5310d093061779e8d5e9a2c91da044c9ed334cf2 Mon Sep 17 00:00:00 2001 From: James Morse Date: Thu, 3 Oct 2019 18:01:27 +0100 Subject: [PATCH] arm64: Fix incorrect irqflag restore for priority masking for compat Commit 46d502a3e81a ("arm64: Fix incorrect irqflag restore for priority masking") added a macro to the entry.S call paths that leave the PSTATE.I bit set. This tells the pPNMI masking logic that interrupts are masked by the CPU, not by the PMR. This value is read back by local_daif_save(). Commit 46d502a3e81a added this call to el0_svc, as el0_svc_handler is called with interrupts masked. el0_svc_compat was missed, but should be covered in the same way as both of these paths end up in el0_svc_common(), which expects to unmask interrupts. Fixes: 46d502a3e81a ("arm64: Fix incorrect irqflag restore for priority masking") Signed-off-by: James Morse Cc: Julien Thierry Signed-off-by: Will Deacon --- arch/arm64/kernel/entry.S | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 84a822748c84e..e304fe04b098d 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -775,6 +775,7 @@ el0_sync_compat: b.ge el0_dbg b el0_inv el0_svc_compat: + gic_prio_kentry_setup tmp=x1 mov x0, sp bl el0_svc_compat_handler b ret_to_user -- 2.39.5