From 4bf5019228cf89e0cbc2cd03627f755d51e3e198 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Thu, 22 Oct 2020 14:35:12 +0800 Subject: [PATCH] fix(imx8m): fix the dram retention random hang on some imx8mq Rev2.0 It seems the DRAM APB clock root slice can NOT work normally if the PLLs is power down in DSM mode. So update this clock slice's setting explicitly to make it work. This piece of code is there for a long while on previous release, so just add it back to align with previous flow. Signed-off-by: Jacky Bai Reviewed-by: Anson Huang Change-Id: I113069494074194e116fdb1229052d2956bf90ea --- plat/imx/imx8m/ddr/dram_retention.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/plat/imx/imx8m/ddr/dram_retention.c b/plat/imx/imx8m/ddr/dram_retention.c index 96591d18b..adcae57b9 100644 --- a/plat/imx/imx8m/ddr/dram_retention.c +++ b/plat/imx/imx8m/ddr/dram_retention.c @@ -18,8 +18,10 @@ #define GPC_PU_PWRHSK (IMX_GPC_BASE + 0x01FC) #define CCM_SRC_CTRL_OFFSET (IMX_CCM_BASE + 0x800) #define CCM_CCGR_OFFSET (IMX_CCM_BASE + 0x4000) +#define CCM_TARGET_ROOT_OFFSET (IMX_CCM_BASE + 0x8000) #define CCM_SRC_CTRL(n) (CCM_SRC_CTRL_OFFSET + 0x10 * (n)) #define CCM_CCGR(n) (CCM_CCGR_OFFSET + 0x10 * (n)) +#define CCM_TARGET_ROOT(n) (CCM_TARGET_ROOT_OFFSET + 0x80 * (n)) #define DRAM_PLL_CTRL (IMX_ANAMIX_BASE + 0x50) @@ -142,6 +144,10 @@ void dram_exit_retention(void) mmio_write_32(CCM_CCGR(5), 2); mmio_write_32(CCM_SRC_CTRL(15), 2); + /* change the clock source of dram_apb_clk_root */ + mmio_write_32(CCM_TARGET_ROOT(65) + 0x8, (0x7 << 24) | (0x7 << 16)); + mmio_write_32(CCM_TARGET_ROOT(65) + 0x4, (0x4 << 24) | (0x3 << 16)); + /* disable iso */ mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, BIT(5)); mmio_write_32(SRC_DDR1_RCR, 0x8F000006); -- 2.39.5